1. Consider the MIPS pipeline discussed in class, suppose the register between t
ID: 3700357 • Letter: 1
Question
1. Consider the MIPS pipeline discussed in class, suppose the register between the Instruction Decode and Execute stages were removed. a. How would this affect the clock cycle? b. What is the speedup of the five stage pipeline vs. this new four stage pipeline? Assume ideal CPI for both cases. c. If the CPl of the five stage pipeline was not ideal, calculate by how much the NOPs would have to be reduced to make the change in the design (from five to four stages) beneficial in terms of performance.Explanation / Answer
Answer:-
If register between Instruction Decode (ID) and Execute Stage (EX) will remove then
(A) Stall or Gap will be created due to register dependency and 3 Cycle pipeline bubble will be created
IF
ID
EX
MEM
WB
IF
Stall
ID
EX
MEM
WB
In the above figure you can see that if register is removed then a 3 cycle stall will be required and 3 Cycle pipeline bubble can be seen. Therefore number of clock cycle increases.
(B). If we asume ideal CPI for both the cases then the speed of new four stage pipeline will increase because this time there is no need of fetching the instruction while in five stage pipeline it has to fetch the instruction so it will take more time.
(C). In case to change the design of pipeline from five to four stage we have to reduce the number of NOP by one (1) i.e. in four stage pipeline the required NOP will be 2.
IF
ID
EX
MEM
WB
IF
Stall
ID
EX
MEM
WB
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