Academic Integrity: tutoring, explanations, and feedback — we don’t complete graded work or submit on a student’s behalf.

3. Consider ADDI instruction from LEGv8 ADDI X2, X 1, #8 // Add 8 to XI and stor

ID: 3703002 • Letter: 3

Question

3. Consider ADDI instruction from LEGv8 ADDI X2, X 1, #8 // Add 8 to XI and store result in X2 The binary representation of this instruction is shown below Rn 5 bits opcodeimmediate 10 bits Rd 12 bits 5 bits In the case of our example, Opcode = 1000000100 (10 bits) Immediate 0000 0000 1000 (12 bits) R, = 00001 (5 bits representing X1) R 00010 (5 bits representing X2) Show the values for all the control signals (each signal is either a zero or a one), and the ALU control (which ALU operation is executed) For this (and most of the problems) we will use the datapaths and control paths shown on page 282 (figure 4.23)- also shown below. Also, we will use the following for ALU control (to specify which operation is performed by the ALU

Explanation / Answer

addi Instruction

ADDI

Include Immediate Word

MIPS Architecture Extension: MIPS I

Configuration:

ADDI rt, rs, quick [I-type]

ADDI               rs               rt              immediate

001000 01010           01010        000000000001000

6    5    16

Reason:

To add a steady to a 32-bit number. On the off chance that flood happens, at that point trap.

Depiction:

rt <-rs + quick

The 16-bit marked quick is added to the 32-bit an incentive in GPR rs to deliver a 32-bit result. On the off chance that the expansion brings about 32-bit 2's supplement math flood then the goal enroll isn't altered and an Integer Overflow special case happens. In the event that it doesn't flood, the 32-bit result is put into GPR rt.

Confinements:

On 64-bit processors, if GPR rs does not contain a sign-broadened 32-bit esteem (bits 63..31 equivalent), at that point the consequence of the task is unclear.

Activity:

in the event that (NotWordValue(GPR[rs])) at that point UndefinedResult() endif

temp <-GPR[rs] + sign_extend(immediate)

in the event that (32_bit_arithmetic_overflow) at that point

?SignalException(IntegerOverflow)

else

?GPR[rt] <-sign_extend(temp31..0)

endif

Special cases:

Whole number Overflow

Programming Notes:

ADDIU plays out a similar math task be that as it may, does not trap on flood.

Hire Me For All Your Tutoring Needs
Integrity-first tutoring: clear explanations, guidance, and feedback.
Drop an Email at
drjack9650@gmail.com
Chat Now And Get Quote