Problem 1 Consider the following assembly language code: 10: add SR3,SR1,SRO; I1

Question

Problem 1 Consider the following assembly language code: 10: add SR3,SR1,SRO; I1: lw SR2,200(SR1); 12: bez SR4,R2,Label 1 13: sw R2, 100 (SR4); 14: sub SR9,SR3,SR2; IISUB R9- R3-R2 15: add SR4,SR9,SR6; 16: addi SR2,SR1,12; 17: lw SR1, 200(SR2); I/LDW R1 -MEMIR2+200] R1; 18: lw $R7,120(SR1); Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Inse ADD R3-R1+RO /LDW R2 MEMIR1 +100] //If $R4 = SR2 Go to Labell //STW MEMIR4 + 1001 = R2 ADD R4- R9R6 /ADDI R2- R1+12; ILDW R7 MEMIR1 + 120]; . Assume that there two levels characters IF, ID, EX, MEM, WB for each instruction in the boxes of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding unit detects (arrow between the stages handing off the data and the stages receiving the data). (a) What is the final execution time of the code? 10 12 16 The final execution time is (b) Verify your answer in part (a)

Explanation / Answer

I0 - Executed sequentially

I1- IF will start at T1 because I0 is fetching at T0. after I0 fetch is over I1 will start at T1. And no dependency between I0 and I1. without any stall I0 and I1 execute

I2- at T2 I2 will be fetched. I2 depends on I1. R2 value should be loaded. then only it is used for I2. so ID stage stall for two time unit. since forwarding technique is used, EX stage of I1 provides the result to I2 before writing into register.

I3- empty box represents stalls. and after IF over waits for ID fetch of previous to complete and then starts so it make stalls

and this procedure continuous for all instructions and finally it takes totally 15 clock cycles to complete the instructions

T1 T2 T3 T4 T5 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 I0 IF ID EX M WB I1 IF ID EX M WB I2 IF ID ID EX M WB I3 IF ID ID EX M WB I4 IF ID EX M WB I5 IF ID EX M WB I6 IF ID EX M WB I7 IF ID EX M WB I8 IF ID EX M WB

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