Question 3 120 Points]-RAM A 128K x 8 RAM chip uses coincident decoding by split
ID: 3705769 • Letter: Q
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Question 3 120 Points]-RAM A 128K x 8 RAM chip uses coincident decoding by splitting the column select. Part (a) (4 points) Assuming that the RAM cell array is square, what is the slze of the row decoder? internal decoder into row select and Part (b) (4 points) Assuming that the RAM cell array is square, what is the size of the column decoder? Part (c) (4 points) A DRAM has a refresh interval of 60 ms and has 16384 between refreshes for distributed refresh? rows. What is the interval Part (d) (4 points) Assuming the time to perform a single refresh is sOns, what is the total time required out of the 60 ms for a refresh of the entire DRAM? Part (e) (4 points) What is the minimum number of address pins on the DRAM? Question 4-Register File/RAM [12 Points] The figure below is a register file connected with a RAM. Suppose our register file has 8 registers and each register can hold 16 bits data, fill in the correct values for n and k. D data WR-Write D address Register File A address B addrass RAM ADRS DATA OUT 5V-C5 MW WR bits nis k is bits The RAM block uses A data from register file as its address bus and B data as its data bus. The RAM's size is Bytes. (You can write it in exponential form, eg. 2 .)Explanation / Answer
a) The memory has 220 bits.
So, there will be 210 = 1024 rows and columns.
This means that the row decoder will require 10 bits.So, it will be a 10 X 1024 decoder.
b) The memory has 128K = 217 words .So, the address will contain 17 bits . Now 17 - 10 = 7 bits.
Therefore the column decoder will require 7 bits .So, it will be a 7 X 128 decoder.
c) Interval between refreshes for distributed refreshes = refresh interval / number of rows = 60/16384 = 0.003662 ms.
d) Total time required = time to perform a single refresh * number of rows = 50*16384 = 819200 ns.
e) Now number of rows = 16384 = 214.
Therefore minimum 14 address pins will be required.
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