4. (10 points) For standard five-stage pipeline datapath a) Explain the stall-on

Question

4. (10 points) For standard five-stage pipeline datapath
a) Explain the stall-on-branch strategy for implementing the ‘beq’ instruction. Explain this strategy
for the two approaches of implementing the ‘beq’ (in ID stage and in MEM stage). Answer the
items in the list below.
b) Explain the branch prediction strategy for implementing the ‘beq’ instruction. Explain this
strategy for the two approaches of implementing the ‘beq’ (in ID stage and in MEM stage).
Answer the items in the list below.
c) Explain the delayed branch strategy for implementing the ‘beq’ instruction. Explain this strategy
for the two approaches of implementing the ‘beq’ (in ID stage and in MEM stage). Answer the
items in the list below.
• How many ‘nops’ are used if the branch is taken?
• How many ‘nops’ are used of the branch is not taken?
• Is this solution always applicable? Explain.

4. (10 points) For standard five-stage pipeline datapath a) Explain the stall-on-branch strategy for implementing the 'beq' instruction. Explain this strategy for the two approaches of implementing the 'beq' (in ID stage and in MEM stage). Answer the items in the list below. b) Explain the branch prediction strategy for implementing the 'beq' instruction. Explain this strategy for the two approaches of implementing the 'beq' (in ID stage and in MEM stage). Answer the items in the list below c) Explain the delayed branch strategy for implementing the "beq' instruction. Explain this strategy for the two approaches of implementing the 'beq" (in ID stage and in MEM stage) Answer the items in the list below. How many nops' are used if the branch is taken? How many 'nops' are used of the branch is not taken? Is this solution always applicable? Explain.

Explanation / Answer

a) The stall-on-branch places ‘nops’ until the address of branch is known, at that time it modifies PC and start the execution of next instruction. In ID stage, there is one ‘nops’ inserted irrespective of the branch is taken or not. For the MEM stage, there are two ‘nops’ inserted irrespective of the branch is taken or not. This solution is always applicable because all that it has to do is the insertion of ‘nops’.

b) The branch prediction infers that the branch will not be taken, and the execution of the next instruction will be started. The execution will be continued fast in case of branch is not taken, and if the branch is taken, the instruction is removed and the branch instruction is started. In ID stage, if branch is taken then one ‘nops’ is used and if branch is not taken then no ‘nops’ are used.In the MEM stage, if branch is taken two ‘nops’ are used and if branch is not taken no ‘nops’ are used. This solution is always applicable because only thing it has to do is to continue with instruction PC+4, and if branch is taken then jump to the branch address in order to start the instruction.

c) The delayed branch is an instruction which does not modify the ‘beq’ instruction, in the place where the ‘nops’ would be. So for both the ID stage and the MEM stage, no ‘nops’ are required whether the branch is taken or not. This solution is not always applicable because there are chances when no instruction can be put in the ‘nops’ space, so a ‘nops’ would still end up having to be used.

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