Consider the following code fragment, and assume that it is executed on a 5-stag

Question

Consider the following code fragment, and assume that it is executed on a 5-stage pipelined datapath like MIPS:

I1: add r5, r2, r1

I2: lw r3, 4(r5)

I3: lw r2, 0(r2)

I4: or r3, r5, r3

I5: sw r3, 0(r5)

1) If the processor has forwarding, how many NOPs need to be inserted in this code fragment to ensure correct execution?

A. 0

B. 1

C. 2

D. None of the above

2) If register renaming is used for the code fragment, how many physical registers do we need for the architectural register r3?

A. 1

B. 2

C. 3

D. None of the above

3) What types of dependencies exist regarding the register r3?

A. RAW

B. WAW and RAW

C. WAW, RAW and WAR

D. None of the above

Explanation / Answer

Solution:

1)

C. 2

2)

A. 1
3)

B. WAW and RAW.

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