You know that a Configurable Logic Block (CLB) in our FPGA is programmed to impl

Question

You know that a Configurable Logic Block (CLB) in our FPGA is programmed to implement a combo logic function by loading a f/f register and then using the register as a Look-Up Table (LUT). This HW is to write VHDL code for the behavior of a very small CLB using entity MUX as a component HW6 (5pts) The MUX logic and its icon are in fig. 1 58 Figure 1: MUX schematic and its icon Implement the MUX in the following VHDL by completing the one assignment statement for Output port g: VHDL for HW6: entity MUX Library ieee; Use ieee.std_logic 1164.all; entity MUX is port (S,A,B: in std.logic; g: out std_logic); architecture behavorial of MUX is begin g

Explanation / Answer

VHDL for MUX:

VHDL for HW6: entity MUXl

Library ieee;

Use ieee.std_logic_1164.all;

entity MUX is

port(S,A,B: in std_logic;

g: out std_logic);

end MUX;

architecture behavorial of MUX is

begin

g<=(A AND (NOT S)) OR (B AND S);

end bahavorial;

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