.Scheduling instructions can remove some hazards that cannot be handled by hardw

Question

.Scheduling instructions can remove some hazards that cannot be handled by hardware without pipeline stalls. Assume a 5-stage MIPS processor has all the forwarding paths needed for better performance. The conditional branch is resolved in the ID stage. The branch is delayed and the instruction in the branch delay slot is always executed (i.e., you can place an instruction in the branch delay slot to save a cycle).

a) Schedule the instructions in the following MIPS code to reduce pipeline installs.

b) Draw a pipeline diagram from the IF stage of the first instruction to the IF stage of the same instruction in the next iteration.

I2: I3: I4: I5: I6: I7: I8: I9: ?t0, $t0, $t1 add SW addi addi addi bne ?s0, $s0, 4 ?s1, $sl, 4 $s2, $s2, 1 $s2, $s3, I1

Explanation / Answer

Answer is as follows :

a) Instruction Scheduling/Rearrangement to reduce data hazards and pipeline installs :

lw $t0, ($s0)

lw $t1 ,($s1)

addi $s1,$s1,4

add $t0,$t0,$t1

addi $s2,$s2,1

sw $t0,($s0)

addi $s0,$s0,4

bne $s2,$s3,I1

The above sequence of instructions helps us to reduce the pipeline installs.

b) Pipeline Diagram for generating sequence :

lw $t0, ($s0)

lw $t1 ,($s1)

addi $s1,$s1,4

add $t0,$t0,$t1

addi $s2,$s2,1

sw $t0,($s0)

addi $s0,$s0,4

So the instruction reduces the pipeline installs from 14 to 12 cycles with rearrangement.

14 cycles are occur before rearrangement.

In this there is only one hazard from sw $t0,($s0) to addi $s0,$s0,4

So hazards are also less there.

F = Instruction Fetch

ID = Instruction Decode

EX = Exeecute Instruction

MEM = Memory Operations

WB = Register Write.

if there is any query please ask in comments...

1 2 3 4 5 6 7 8 9 10 11 12 13 14

lw $t0, ($s0)

IF ID EX MEM WB

lw $t1 ,($s1)

IF ID EX MEM WB

addi $s1,$s1,4

IF ID EX MEM WB

add $t0,$t0,$t1

IF ID EX MEM WB

addi $s2,$s2,1

IF ID EX MEM WB

sw $t0,($s0)

IF ID EX MEM WB

addi $s0,$s0,4

IF ID EX MEM WB bne $s2,$s3,I1 IF ID EX MEM WB

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