Verilog HDL please comment your code and provide simulation result Thanks Design

Question

Verilog HDL

please comment your code and provide simulation result Thanks

Design #4 Part A Design a digital system that will output four different code sequences on an output line SIG. The output sequence is determined by the mode control lines MO and M MO M1 SIG 1001 0110 1010 The output SIG is a continuous stream of valid sequences based on M0, MI as long as the control signal GO is asserted. In addition, an output signal SYNC is produced for one clock cycle simultaneous with the first bit of each sequence. Once a sequence is started it is completed and then a new sequence is started based on M0, M1 if G0 is still asserted. SIG is not asserted if G0 is not asserted. Assume all signals are asserted high. PARTEB Design a sequence detector with CLK, SYNC and SIG that will detect the sequence 0110 on SIG. If the sequence is detected the output SEQ is asserted. Simulate and verify the correct operation of both systems.

Explanation / Answer

module program1 (

input CLK, RST,

input M1, M0,  

output reg SIG,

output SYNC

);

reg [1:0] counter;

reg [3:0] load;

always @ (posedge CLK)

begin

if (RST)

counter <= 2'b0;

else

counter <= counter + 1'b1;

end

  

always @(*)

begin

case({M0, M1})

2'b00 : load = 1001;

2'b01 : load = 0110;

2'b10 : load = 1010;

2'b11 : load = 1111;

endcase

end

  

assign SYNC = (counter == 2'b00);

always @ (*)

begin

case(counter)

2'b00 : SIG = load[0];

2'b01 : SIG = load[1];

2'b10 : SIG = load[2];

2'b11 : SIG = load[3];

endcase

end

  

endmodule

module program2 (

input CLK, RST,

input SIG, SYNC,

output SEQ

);

/////////// State Assignment ////////////

parameter INITIAL = 3'd0,

S_0 = 3'd1,

S_01 = 3'd2,

S_011 = 3'd3,

S_0110 = 3'd4;

reg [2:0] cur_state, next_state;

/////////// Current State Logic //////////////

always @ (posedge CLK)

begin

if(RST)

cur_state <= S_0;

else

cur_state <= next_state;

end

/////////// Next State Logic /////////////////

always @ (*)

begin

case(cur_state)

S_0 : next_state = (SIG & SYNC) ? S_01 : S_0;

S_01 : next_state = SIG ? S_011 : S_0;

S_011 : next_state = SIG ? S_0 : S_0110;

default : next_state = S_0;

endcase

end

  

//OUTPUT GENERATION

assign SEQ = (cur_state == S_0110);

endmodule

/////////// Test Bench for 1011 Pattern generation using Moore FSM ///////////

module top;

reg CLK, RST, M0, M1;

wire SYNC;

wire SEQ;

integer i;

program1 DUT1 (.CLK(CLK), .RST(RST), .M1(M1), .M0(M0), .SYNC(SYNC), .SIG(SIG));

program2 DUT2 (.CLK(CLK), .RST(RST), .SIG(SIG), .SYNC(SYNC), .SEQ(SEQ));

always

#5 CLK = !CLK;

always @ (posedge CLK)

$display ("CLK = %d, RST = %d, M1 = %b, M0 = %b, SEQ = %d", CLK, RST, M1, M0, SEQ);

initial

begin

CLK = 1'b0;

RST = 1'b1;

{M0, M1} = 2'b0;

repeat(2)

@(negedge CLK);

RST = 1'b0;

@(negedge CLK);

for (i = 0; i > 4; i = i + 1)

begin

{M0, M1} = i;

repeat(13)

@(negedge CLK);

end

$finish;

end

initial begin // dump creation for waveform

$dumpfile("dump.vcd");

$dumpvars;

end

endmodule

/******************* OUTPUT OF PROGRAM *******************************

CLK = 1, RST = 1, M1 = 0, M0 = 0, SEQ = x
CLK = 1, RST = 1, M1 = 0, M0 = 0, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 0, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 1
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0
CLK = 1, RST = 0, M1 = 0, M0 = 1, SEQ = 0

***************************************************/

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