There are different forms of addressing available with ARM. As the ARM philosoph
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Question
There are different forms of addressing available with ARM. As the ARM philosophy is to reduce the number of instructions needed to execute a program, we have many different addressing modes available in ARM. There are four addressing modes that are available in ARM that we’ll look at:
Immediate
Scaled register
Scaled register pre-indexed
PC-relative
Research to review what each of those addressing modes represents. For each of the ARM addressing modes, provide an example of an ARM instruction that uses that particular addressing mode. What is the instruction format type of each of the instructions that you provided?
Compare and contrast each of the ARM addressing modes. What are the benefits and drawbacks of each? Write a snippet of ARM code that shows the benefits and drawbacks. How do these methods compare to other instructions sets?
Must be 500 words
Please make copy paste available
Explanation / Answer
1.) Immediate Addressing mode: An instruction deploying immediate addressing mode has the following instruction syntax :
Opcode Operand.
An immediate operand will be a constant value or an expression. This instruction specifies that the operand is hard-coded and is used like that, that is, we do not have to fetch the operand. The instruction is often executed on the register or accumulator address provided or on the current working register.
Ex: MOV R0, #15; This instructs the processor to move the const value 15 to register R0.
2.) Scaled Register Addressing Mode:
Ex : load reg base index.
In scaled addressing mode, the effective address is dynamically calculated according to the data type.This addressing modes are especially useful when addressing arrays, but are not limited to that only. This mode dynamically 'scales' the value in 'index' register so as to accomodate the size of each array element.If we take a float integer type array the index will be scaled by multiplying 4 (considering the float datatype uses 4bytes of space).
Here, base and index are any 32 bit registers.
Ex : (Consider esi contains 4), then
MOV al, 1000h[esi*8]; Loads al from what is at location 1020h. (where *8 is the scaling).
3.) Scaled register with pre-index:Scaled register with pre-index, as we know that pre-indexing corresponds to indirect addressing mode and pre corresponds that the generated address is used immediately, can be seen as scaled addressing mode with an offset value. Thus, the memory location instead of being directly supplied is stored in other register and this is then specified to be used to access memory.
Ex : MOV al, 8[EAX][ESI*4], here 8 is the offset and if EAX contains 1000h, and esi contains 4, we can work out the maths and the effective address comes out to be 1018h. Thus the instruction decodes to: load al from what is at location 1018h.
Here the offset is used to diplace the calculate address by 'offset places' and this becomes the effective address.
The use of the square brackets ([])distinguishes a normal register from a memory location
4.) PC-relative : Relative addressing modes, as derived from displacement addressing, uses Program counter in place of registers. That is, the data is is referenced in the instruction using the offset from PC. This is a useful mode that is often selected by the assembler as a first choice when the user does not explicitly specify any other mode. It also results in an instruction that does not require relocation by the loader. Effective address is calculated as:
EA= disp+ PC.
Now, Program counter holds the address of the next instruction at runtime, and the displacement can be calculated with the help of Location counter, which is a compiler maintained variable and points to the instruction currently being compiled.
Thus disp= EA-PC, or
disp = EA - LC- size of current instruction. (as, PC=holds address location of next instruction= LC + size of current instruction).
With this formula, we can explain that the displacement is essentially the distance between the instruction and its operand, and this distance does not depend on the start address of the program. Essentially,this mode generates position independent code and an instruction using it does not have to be relocated.
Ex: JMP B.
Assuming that the JMP instruction is assembled and loaded in memory location 60 and the value of symbol B is address 10. Thus disp= 10-60-1.
The value here comes negative and this shows that the operand precedes the instruction.
Instruction format types:
The MOV instruction has the following general representation :
MOV register, immediate value.
MOV register, register.
MOV memory, register and vice versa.
MOV memory, immediate.
The JMP instruction transfers program control to a different point in the instruction stream without recording return information. The destination (target) operand specifies the address of the instruction being jumped to. This operand can be an immediate value, a general-purpose register, or a memory location.
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