Problem A. Assuming that there is no structure hazard in the parallel execution

Question

Problem A. Assuming that there is no structure hazard in the parallel execution of two different stages, please identify (1) the type of hazard (Structure hazard, Data hazard, or Control hazard) and (2) in which stage of the 2nd instruction such hazard occurs in the pipelined implementation of two instructions.

(c)

LDR R1, [R3, R6]

;it’s executed in five stages: IF, ID, EX, MEM, WB

ADD R4, R1, #5

;it’s executed in four stages: IF, ID, EX, WB

(c)

LDR R1, [R3, R6]

;it’s executed in five stages: IF, ID, EX, MEM, WB

ADD R4, R1, #5

;it’s executed in four stages: IF, ID, EX, WB

Explanation / Answer

1) Data hazard: In instruction 2, 5 is added to R1 which should be first written by instruction 1 then only instruction 2 can access and get R1.

2)

Instruction

1

2

3

4

5

6

Instruction 1

IF

ID

EX

MEM

WB

Instruction 2

IF

ID

EX

MEM

In instruction 2, in ID stage(3) hazard is occurred because in ID(decode) stage instruction is decoded and registers are accessed to get values which is R1, but till now instruction 1 has not written R1(is done in 5) and thus data hazard occurred.

Instruction

1

2

3

4

5

6

Instruction 1

IF

ID

EX

MEM

WB

Instruction 2

IF

ID

EX

MEM

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