4.8.3: If we can split one stage of the pipelined datapath into two new stages,
ID: 3714705 • Letter: 4
Question
4.8.3: If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?
4.8.4: Assuming there are no stalls or hazards, what is the utilization of the data memory?
4.8.5: Assuming there are no stalls or hazards, what is the utilization of the write- register port of the "Registers" unit?
EX 150ps MEM 300ps WB 200ps ID IF 250ps 350ps SW beg alu 45% 15% 20% 20%Explanation / Answer
Solution:
4.8.3
Split ID into two stages with 175ps
New clock cycle time = 300ps
Because this is the newest longest stage in the data path.
4.8.4
Data memory is utilized by 1w and sw instructions, so the utilization is 35% of the dock cycle.
4.8.5
Write-register port may be used by ALU and 1w instructions, so the utilization is 65% of the clock cycle.
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