on nap ter-\' or your text 00K. ype your answers, response for each in a report,
ID: 3715867 • Letter: O
Question
on nap ter-' or your text 00K. ype your answers, response for each in a report, and submit the report through Black Board. Possible score point for each exercise is also mentioned bellow. Show your work and cite accordingly ifwhere applicable Question 1. (20 points) Consider a cache with 64 blocks and a block size of 8 bytes. Using direct memory mapping, to what block number does byte address 1024 map? Question 2. (15+15-30 points) a. Define the steps to be taken on an instruction cache miss. b. Distinguish among, write through and write back Question 3.(20+10 30 points) a. Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 10%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 40%. b. Find the average memory access time(AMAT) for a processor with a 1 ns clock cycle time, a miss penalty of 40 clock cycles, instruction miss rate of 10%, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls Question 4. (20 points) Configure an eight-block cache as direct mapped, two-way set associative, four-way set associative, and fully associative Book: Computer Organization and Design: The Hardware/Software Interface, Patterson & Hennessy, Morgan Kaufmann, 5th Edition. Good Luck! 410:40 PM 4/24/2018Explanation / Answer
Solution:
Note: The first question is done as per Chegg guidelines, please repost others.
1)
Number of blocks in the cache = 64 blocks
Number of bits required to address each block is = 6-bits
block size = 8 bytes
1024 in binary is 10000000000
1024 mod 64 = 0
It will be mapped to 0th block in the cache.
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