The verilog file, counters.v, contains the four counters, a count by 3, a count

Question

The verilog file, counters.v, contains the four counters, a count by 3, a count by 5, a count by 3 that clamps at the largest value, a count by 5 that clamps at tehe largest value. The test bench is tb_counters.v.

The next state logic of each counter is described using behavioural code, replace this code with combination/arithmetic description.

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The next state logic of each counter is described using behavioural code, replace this code with combination/arithmetic description.

Explanation / Answer

Answer:

counters.v: See the updated code below:

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`timescale 1ns / 1ns

module dff( q, d, clk);
    parameter N = 8;
    output reg [N-1:0] q;
    input [N-1:0] d;
    input clk;

    always @(posedge clk) begin
        q = d;
    end
endmodule

module countby3( count, reset, clock );
    output [5:0] count;
    input reset, clock;
    wire [5:0] count_d;

    dff #(6) state( count, count_d, clock);

    // replace with arithmetic and/or combinational logic
    //assign count_d = reset ? 0 : count + 3;
   //See the description below:
   if (reset)
       count_d = 0;
   else
       count_d = count + 3;  
endmodule

module countby3clamp( count, clamp, reset, clock );
    output [5:0] count;
    output clamp;
    input reset, clock;
    wire [5:0] count_d;

    dff #(6) state( count, count_d, clock);

    // replace with arithmetic and/or combinational logic
    //assign clamp = count == 63;
   //See the description below:
   if (count == 63)
       clamp = 1;
   else
       clamp = 0;
    //assign count_d = reset ? 0 : count + (clamp ? 0 : 3);
   //See the description below:
   if (reset)
       count_d = 0;
   else
       begin
           if (clamp)
               count_d = count + 0;
           else
               count_d = count + 3;          
       end
endmodule

module countby5( count, reset, clock );
    output [5:0] count;
    input reset, clock;
    wire [5:0] count_d;

    dff #(6) state( count, count_d, clock);

    // replace with arithmetic and/or combinational logic
    //assign count_d = reset ? 0 : count + 5;
   //See the description below
   if (reset)
       count_d = 0;
   else
       count_d = count + 5;
endmodule

module countby5clamp( count, clamp, reset, clock );
    output [5:0] count;
    output clamp;
    input reset, clock;
    wire [5:0] count_d;

    dff #(6) state( count, count_d, clock);

    // replace with arithmetic and/or combinational logic
    //assign clamp = count == 60;
   //See the description below
   if (count == 60)
       clamp = 1;
   else
       clamp = 0;
    //assign count_d = reset ? 0 : count + (clamp ? 0 : 5);
   //See the description below
   if (reset)
       count_d = 0;
   else
       begin
           if (clamp)
               count_d = count + 0;
           else
               count_d = count + 5;
       end
endmodule

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