A computer system has byte-addressable memory and uses a paged virtual memory sy

Question

A computer system has byte-addressable memory and uses a paged virtual memory system, using 128-byte pages. It uses a 16-bit virtual address and a 14-bit physical address. Its Translation Lookaside Buffer (TLB) is 4-way set-associative and has a total of 16 entries. It uses an L1 cache which is physically addressed and direct mapped, with 4 bytes per cache line and a total of 16 cache sets.

a) Show how the virtual address is divided between the Virtual Page Number and the Virtual Page Offset.

b) Show which bits of the virtual address are used and how they are used for accessing the TLB.

c) Show which bits of the physical address are used for the Physical Page Number and the Physical Page Offset.

d) Show which bits of the physical address are used and how they are used when looking for the data in the L1 cache.

e) Given a virtual address 0xA234

i. What is the Virtual Page Number?

ii. What is the Virtual Page Offset?

iii. What is the TLB index?

iv. What is the TLB tag?

Explanation / Answer

As per the given data in the question, we have

Physical address space = 214 bytes

Virtual Address space = 216 bytes

solution (a)

the no of bits that are requires to locate the byte within the page are called offset bit

Page size = 128 bytes = 27 bytes

No of bits required for offset = 7 bts

No of pages in virtual address space = 216/27 = 29

No. of bits required for pages = 9

So, the 16 bits of virtual address space are divided into two groups, virtual page number having 9 bits and virtual page number offset having 7 bits

solution (b)

It is given in the question that TLB is 4 way set associative and has a total of 16 entries.

4 way set associatives means TLB is divided into sets of 4. So, there will be a total of 4 sets.

2 bits of the virtual addres space will be used to locate the entry within the set and 2 bits for index of the TLB. Rest of the bits will be used for offset

solution (c)

Physical address space = 214 bytes

Page size = 128 bytes = 27 bytes

No of bits required for offset = 7 bts

No of pages in physical address space = 214/27 = 27

bits of physical address space are divide into two groups of equal size having 7 bits each, first seven bits are used for physical page number and next 7 bits are used for physical page offset

solution (d)

In the cache memory, there are 16 sets or 24 sets, which means 4 bits will be required to identify the set or lines.

each line(set) of the cache has 4 bytes capacity,

so, total size of cache = 16 * 4 = 64 bytes = 26 bytes

no of blocks in main memory = 214/26 = 28

8 bits are required for block and 6 bits for block offset.

out of 8 bits of the bock, we require 4 bits to identify the line and rest of the 4 bits for the tag.

solution (e)

virtual address ==>> 0xA234

0x represents it is a hexadecimal number, converting it to decimal, we get

1010 0010 0011 0100

i) virtual page number is represented by first 9 bits(see sol(a)), so.

virtual page number = 101000100

ii) virtual page offset is represented by last 7 bits(see sol(a)). so,

virtual page offset = 0110100

iii) TLB index is represented by 3rd and 4th bits (see sol (b)), so,

TLB index = 10

iv) TLB tag is represented by first 2 bits(see sol(b)). so,

TLB tag = 10

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