Suppose a main memory access requires 30ns, the page fault rate is .01%, it cost

Question

Suppose a main memory access requires 30ns, the page fault rate is .01%, it costs 12ms to access a page not in memory (this time includes the time necessary to transfer the page into memory, update the page table, and access the data).

Also suppose a TLB hit requires 7ns, the cache miss rate is 3%, the TLB hit rate is 95%, a cache hit requires 15ns. On a TLB or cache miss, the time required for access includes a TLB and/or cache update, but the access is not restarted. On a page fault, the page is fetched from disk, all updates are performed but the access is restarted. All references are sequential (no overlap, nothing done in parallel)

a) Calculate the time for a TLB hit and a cache hit.

b) Calculate the EAT (effective access time) for a TLB hit. Do not calculate the entire EAT formula for a 3-level memory hierarchy. Just focus on the first component, where there is a TLB hit. So you would consider the TLB hit ratio, Cache hit ratio, cache miss ratio, TLB access time, cache access time, and main memory access time.

Explanation / Answer

Solution:

->TLB works as a cache for such mapping like the operating system uses virtual memory and page tables maps these virtual address to physical address,

.

program >>> TLB >>> cache >>> Ram

->A program search for a page in TLB, if it doesn't find that page it's a TLB miss and then further looks for the page in cache.

->If the page is not in cache then it's a cache miss and further looks for the page in RAM.

->If the page is not in RAM, then it's a page fault and program look for the data in secondary storage.

So, typical flow would be

->Page Requested >> TLB miss >> cache miss >>main memory>> page fault >> looks in secondary memory.

Here,given data is that,

Main memory access time= 30 ns

Page fault rate=.01%

page fault service time= 12ns

TLB access time=7 ns

TLB hit rate= .95%

TLB miss rate =1-.95=.05%

cache access time = 15 ns

cache miss rate= .3%

cache hit rate = 1-.3=.97%

So,

TLB HIT TIME= 7 ns

   cache hit time = TLB hit rate TLB access time + TLB miss rate ( TLB access time + cache hit time)

                  = .95 7 + .05 (7+15)

CACHE HIT TIME    = 7.75 ns

b) EAT for TLB hit= 7ns

   Total EAT = TLB hit rate ( TLB access time + Cache hit rate cache access time + cache miss rate (cache + main memory access time))+ TLB miss rate ( TLB access time + main memory access time + cache hit rate cache access time + cache miss rate ( cache + main memory access time))

= .95 *( 7 + (.97*15) + .03(15+30))+ .05*(7+30+(.97*15) + .03 ( 15 + 30))

EFFECTIVE ACESS TIME=24.4 ns

Therefore our required values are determined

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