Designing register file and implimenting reg file and ALU together using Verilog

Question

Designing register file and implimenting reg file and ALU together using Verilog.

ALU code from lab 5

1. Design a register file as shown in fig1. The memory should be only written with value given by write_data when regwrite is enabled at the location given by write address(Wa). The register zero should always be zero; it should not hold other content. Write a test bench to test the behavior of the register file that you have designed. Initially initialize all the memory location to some value. Use for loop to initialize memory location. After initializing all memory, read the content of memory in two outputs reg1 and reg2. The read address for output reg1 and reg2 is given by ra1 and ra2 respectively. Clk regwrite ra1 ra2 32 reg1 32 32 register file 32 write_data 32 Wa reg2 Fig1. Register File

Explanation / Answer

module regfile(input clock, input [2:0] address, input en_write, inout [7:0] data);
reg [7:0] registers[7:0];
always @(posedge clock)
    if (en_write)
        registers[address] <= data;
    else
        out_val <= registers[address];
reg [7:0] out_val;
assign data = en_write ? 8'bz : out_val;

endmodule

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