3. Consider a simple in-order processor with the following characteristics: An i

Question

3. Consider a simple in-order processor with the following characteristics:

An instruction can issue if all of its dependencies are satisfied

Consists of a pipeline where one instruction is issued at each cycle if possible.

There is no limit to the number of functional units.

Given the following sequential list of instructions and instruction latencies:

A. load $r2 = 4[$r1]

B. sub $r2 = $r2, $r5

C. store 8[$r1] = $r2

D. add $r1 = $r1, 4

E. store 4[$r6] = $r1

In the code snippet above, offset[register] is a type of memory addressing mode. The address is

computed as the sum of the offset and the value present in the register.

Instruction Latency

add 2

sub 2

load 3

store 4

I. What is the CPI for the sequential code execution? CPI is defined as the ratio of total number of cycles taken for execution to the number of instructions executed.

II. Say we add register renaming to the processor, can the CPI be improved through scheduling instructions differently? If so, explain how and show the new schedule and

the improved CPI value. (Note: Be careful about memory).

Explanation / Answer

I. Above instructions when executed sequentially (needs to be executed sequentially) sums up to 3 + 2 + 4 + 2 + 4 = 15 clock cycles (latency).

Clock cycles per instruction = total clock cycles / total instructions = 15 / 5 = 3

II. R1 can be copied to a new register say R7 using a LOAD operation.

load $r7 = $r1

On a multi pipeline system, operations LOAD R7, D & E can be parallely executed saving 6 cycles but at the cost of 1 load operation and one new register.

New latency = 15 - 6 = 9

New CPI = 9/5 = 1.8

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