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Using a combination of Modelsim and Quartus, implement an ALU that implements th

ID: 3746494 • Letter: U

Question

Using a combination of Modelsim and Quartus, implement an ALU that implements the following functions:

OpCode                Output

0                               A

1                               B

2                              A-B

3                              A+B

4                              Not A

5                              Not B

6                              Shift A left by 2 bits (× 4)

7                              Sign Shift A right by 2 bits (÷ 4)

8                              Shift B left by 2 bits (× 4)

9                              Sign shift B right by 2 bits (÷ 4)

10                             A and B (bitwise AND)

11                            A xor B (bitwise XOR)

Other                      ERROR

Questions,

Implement via behavioral design (VHDL)

Simulate in ModelSim and test for correct functionality

Change “Bit Depth” to 8 bits, and implement the ALU on the DE2-115 and confirm correct operation.

Explanation / Answer

For this question i will use quartus 2 and modelsim for simulating my code. since u have 12 operations at your disposal so you will need 4 bits selection vector to represent it. So a will be my input 1 and b will be my input 2. both of whichs size will be of 4 bit as per the requirement of the question.... so here i attach the code...

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL; ----needed for shift

entity alu is

Port ( a : in signed(3 downto 0);

b : in signed(3 downto 0);

sel : in STD_LOGIC_VECTOR (3 downto 0);

alus : out signed (3 downto 0));

end alu;

architecture Behavioral of alu is
signal l2 : unsigned (3 downto 0):="0000";
signal l1 : unsigned (3 downto 0):="0000";
signal r2 : signed (3 downto 0):="0000";
signal r1 : signed (3 downto 0):="0000";
begin

process(a, b, sel)

begin

case sel is

when "0000" =>

alus<= a;

when "0001" =>

alus<= b;

when "0010" =>

alus<= a + b;
when "0011" =>

alus<= a + b;

when "0100" =>

alus<= NOT a;

when "0101" =>

alus<=NOT b;
when "0110" =>

l1 <= shift_left(unsigned(a), 2) ;
alus<= signed(l1);

when "0111" =>

r1 <= shift_right(signed(a), 2);
alus<= r1 ;

when "1000" =>

l2 <= shift_left(unsigned(b), 2);
alus<=signed(l2);

when "1001" =>

r2 <= shift_right(signed(b), 2);
alus<= r2;

when "1010" =>

alus<= a AND b;

when "1011" =>

alus<= a XOR b;

when others => NULL;


end case;

end process;

end Behavioral;

this code will meet the needs of the given question. comments are attached with the code are for explanation of the code..

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