1. Write gates HDL module to describe bitwise operations acting on 4-bit busses

Question

1. Write gates HDL module to describe bitwise operations acting on 4-bit busses for basic logic functions.

2. Sketch a schematic of the circuit.

Source Code:

module main;

  reg [3:0]a,b;

wire [3:0]y1,y2, y3,y4, y5;

gates gate( .a(a), .b(b), .y1(y1), .y2(y2), .y3(y3), .y4(y4), .y5(y5) );

initial

    begin

      $dumpfile("dump.vcd");

      $dumpvars(1, main);  

      $display("Time a b a&b a|b a^b ~(a&b) ~(a|b)");

      $monitor("%3d %b %b %b %b %b %b %b",$time, a,b,y1,y2,y3,y4,y5);

      a=11;

      b=6;

      #5 a=1010; b=0101;

    end

endmodule

Explanation / Answer

In your experiment if, the input signal is high that is if it has an constant or variable voltage or amplitude greater than 2.5 then it will be considered as logic 1, and if there is no signal or the amplitue of the signal is below 2.5 then it considered as logic 0.

If the input signal is high then the first inverter inverts the input signal. So, the output of the first inverter will be logic 0. Then the second inverter inverts the output of the first inverter so the output will be logic 1. After that the third inverter inverts the output of the second inverter so that the output will be low. Likewise, the output of all odd numbered inverters is high or logic 1. All even numbered inverters output is low or logic 0.

If the input signal is low then the output of the first inverter will high that logic 1.Then the second inverter inverts the output of the first inverter so the output will be logic 0. After that the third inverter inverts the output of the second inverter so that the output will be high. Likewise, the output of all odd numbered inverters is low or logic 0. All even numbered inverters output is high or logic 1.

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