VHDL for the combinational logic of a sequence detector without clock and reset
ID: 3757395 • Letter: V
Question
VHDL for the combinational logic of a sequence detector without clock and reset
i have the VHDL for the combinational logic code, i just need the testBench code
•NSDecode logic
•Combinational VHDL model (no clk or rst input signals)
•Use a process and case statement
•Use the default signal approach
•Do not forget the others clause in the case statement
•OPDecode logic
•It is possible (and more efficient VHDL) to use a single line Boolean assignment for signal openLock, though use a process with an if statement, and default.
VHDL code for sequence detector
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity seqDet is
Port ( CS : in STD_LOGIC_VECTOR(1 downto 0);
usercode : in STD_LOGIC_VECTOR(1 downto 0);
validcode : in STD_LOGIC;
NS : out STD_LOGIC_VECTOR(1 downto 0) ;
openLock : out STD_LOGIC );
end seqDet;
architecture combinational of seqDet is
begin
NSDecode: process (CS, usercode, validcode)
begin
NS <= CS;
if (validcode) = '1' then
case (CS) is
when "00" =>
if (usercode) = "10" then
NS <= "01";
end if;
when "01" =>
if (usercode) = "11" then
NS <= "10";
end if;
when "10" =>
if (usercode) = "01" then
NS <= "11";
end if;
when others =>
NULL;
end case;
end if;
end process;
end combinational;
some of the code for the testBench (its not finished and needs to be corrected)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- testbench has no inputs or outputs
ENTITY seqDet_TB IS END seqDet_TB;
ARCHITECTURE behavior OF seqDet_TB IS
-- declare the AND2_1 component
COMPONENT seqDet_TB is
Port ( CS : in STD_LOGIC_VECTOR(1 downto 0);
usercode : in STD_LOGIC_VECTOR(1 downto 0);
validcode : in STD_LOGIC;
NS : out STD_LOGIC_VECTOR(1 down to 0);
openLock : out STD_LOGIC
);
END COMPONENT;
-- declare signals connecting stimuli to the
-- Unit Under Test (UUT)
signal CS : in STD_LOGIC_VECTOR(1 downto 0);
signal usercode : in STD_LOGIC_VECTOR(1 downto 0);
signal validcode : in STD_LOGIC;
signal NS : out STD_LOGIC_VECTOR(1 down to 0);
signal openLock : out STD_LOGIC
-- Test nums 0-5. Aids browsing of sim waveform
signal testNo : integer range 0 to 5;
-- assert to highlight end of simulation
signal endOfSim : boolean := false;
BEGIN
-- Instantiate the Unit Under Test (UUT)
-- syntax is internal signal => connecting signal
uut: seqDet PORT MAP
(CS => CS,
usercode => usercode,
validcode => validcode,
NS => NS,
openLock => openLock);
stim_i: process -- Stimulus process
-- variable value change immediately on assignment in process
-- Use tempVec to define the TB i/p signal vector
variable tempVec : std_logic_vector(4 downto 0);
begin
report "%N : Simulation start";
-- Define default input signals and flags
endOfSim <= false;
testNo <= 0;
--AND2In1 <= '1'; -- assert both inputs (logic 1)
--AND2In0 <= '1';
--wait for 10 ns;
--testNo <= 1;
for i in 0 to 31 loop
tempVec := std_logic_vector(to_unsigned(i,5));
validcode <= tempVec(4);
CS <= tempVec(0);
usercode <= tempVec(4);
wait for 10 ns;
end loop;
testNo <= 2;
signalnameA <= '1'; -- deassert both inputs (logic 0)
signalnameB <= '1';
wait for 10 ns;
report "%N : Simulation Done.";
endOfSim <= true;
wait; -- wait forever. Do not rerun the stimulus process (which has no sensitivity list)
end process;
END;
Sequence detector Sequence has 4 states code(1:0) openLock TheseqDet system progresses through states (from an initial state getCode0State) on entry of a precise code sequence on code(1:0), validated by assertion of signal validCode validCo clk Component Symbol rst Signal openLock is asserted in the final (openLockState) state, if the correct code sequence is entered The system remains in the openLockState until assertion and deassertion of signal reset, which puts the system into state getCodeOState CS(1:0) Combinational logic Store current system state Sequential (memory) code(1:0) stateR If an incorrect code is entered in the sequence, the seqDet system remains in the current state and does not return to the getCode0 state. This reduced the CS 1:0 NSDecode2 NS(1:0 validCode rst exity of the de sign though does OPDeco de not result in a very securecode unlocking system. CS(1:0)(. Data Flow Diagram (DFD)Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity moore is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end moore;
architecture Behavioral of moore is
type state is (st0, st1, st2, st3);
signal present_state, next_state : state;
begin
synchronous_process: process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
output_decoder : process(present_state, din)
begin
next_state <= st0; case (present_state) is when st0 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0; end if; when st1 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st2; end if; when st2 =>
if (din = '1') then
next_state <= st3;
else
next_state <= st0; end if; when st3 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st2; end if; when others =>
next_state <= st0; end case; end process; next_state_decoder : process(present_state) begin case (present_state) is when st0 =>
dout <= '0'; when st1 =>
dout <= '0'; when st2 =>
dout <= '0'; when st3 =>
dout <= '1'; when others =>
dout <= '0';
end case;
end process;
end Behavioral;
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