Q1. (a) Consider a processor that uses 6-bits for addressing the memory (byte ad
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Question
Q1. (a) Consider a processor that uses 6-bits for addressing the memory (byte addressable). It has a direct mapped cache that has 4 blocks where a block contains 8 bytes. The processor accesses the memory addresses in the following order:
1, 3
Initially cache is empty and is shown in figure below. Show the state of the cache after two accesses. What is the hit ratio?
(b) Assume a two-way set associative cache that can accommodate 4 blocks of data. The processor accesses the following sequence of block addresses: 0, 4, 5, 2, 0. Identify for each access whether it is a hit or miss. When replacing a block in a cache assume LRU policy.
.
Q2. (a) Consider a 128 bytes of memory, and a direct mapped cache that has eight blocks with 8 bytes per block. Assume memory is byte addressable. What the size of cache is in bits including the space for valid and tag information?
(b) Consider a 220 bytes of memory, and a direct mapped cache that has 32 blocks, where each block contains 16 bytes. How many blocks of main memory are there?
(c) Consider a 220 bytes of memory, and a direct mapped cache that has 32 blocks, where each block contains 16 bytes. Assume memory is byte addressable. What is the size of tag?
Q3. (a) For a data cache with a 92% hit rate and a 2-cycle hit latency, calculate the average memory access latency. Assume that latency to memory and the cache miss penalty together is 124 cycles.
(b) Consider a processor that has a separate data and instruction cache. The data cache is same as described in (a) and 30% of instructions are loads and stores. The instruction cache has a hit rate of 90% with a miss penalty of 50 cycles. Assume the base CPI using a perfect memory system is 1.0. Assume that instruction cache misses and data cache misses never occur at the same time.
(i) Calculate the additional CPI due to the icache stalls.
(ii) Calculate the additional CPI due to the dcache stalls.
(iii) Calculate the overall CPI for the machine.
Valid Tag Data N N N NExplanation / Answer
3.a)
For a data cache with a 92% hit rate and a 2-Cycle hit latency, calculate the average memory access latency. Assume that latency to memory and the cache miss penalty together is 124 cycles
I
The average memory access latency is (hit time) + (miss rate) × (miss time).
Missrate=1-hitrate
hitrate=92/100
missrate=1-o.92
missrate=0.08
hit time=2
misstime=124
– average memory access latency = 2 + 0.08*124
= 11.92 cycles
3.b)
(b) Consider a processor that has a separate data and instruction cache. The data cache is same as described in (a) and 30% of instructions are loads and stores. The instruction cache has a hit rate of 90% with a miss penalty of 50 cycles. Assume the base CPI using a perfect memory system is 1.0. Assume that instruction cache misses and data cache misses never occur at the same time.
(i) Calculate the additional CPI due to the icache stalls.
(ii) Calculate the additional CPI due to the dcache stalls.
(iii) Calculate the overall CPI for the machine.
(i)The additional CPI due to icache stalls = Hit Rate * Hit Latency + Miss Rate* Miss Penalty
Hitrate=90/100=0.9
Hit latency=2
Miss penalty =50
Missrate=1-hitrate
1-0.9=0.1
Hit Rate * Hit Latency + Miss Rate* Miss Penalty
= 0.9*2 + 0.1*50= 1.8 + 5= 6.8
(ii)The additional CPI due to dcache stalls = Hit Rate * Hit Latency + Miss Rate* Miss Penalty
Missrate=1-hitrate
hitrate=92/100=0.92
missrate=1-o.92
missrate=0.08
misspenalty=124
Hit latency=2
0.92*2 + 0.08*124= 11.76
(iii)The overall CPI = 0.3*11.76 + 0.7*1.0 + 1.0*6.8= 11.03
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