3 GHz, 8 stage pipeline, instruction buffers that negate instruction load penalt

Question

3 GHz, 8 stage pipeline, instruction buffers that negate instruction load penalties.

• 25% of instructions are loads, 5% are stores. Branches are 20% and have an average

branch penalty of .3 cycles. All other instructions are ideal (cpi 1) except for memory

access delays.

• 32Kb L1 cache, 500ps access, 8-way associative, write-through (via a buffer, that

eliminates the penalty of writes to lower memory in all but 1/66 cases), not write-
allocate, 1/21 miss rate for Data and a miss rate of 1/42 for Instructions • 1Mb L2

cache, 10ns access, 4-way associative, write-back, write-allocate, 20% miss rate, 10%

dirty

a. For the given instruction mix, what is the cpi?

b. Assume the same CPU but no cache. What is the cpi?

c. What is the speedup we get from cache?

Explanation / Answer

a)                                    cycles

     Loads          25%          3

    branches       20%          3

stores            5%         3

cpi= (3*25+3*20+3*5)/100 =15

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