Help with Verilog Design! Must use five stage pipeline design Should have clk, r

Question

Help with Verilog Design!

Must use five stage pipeline design

Should have clk, rst_n and hlt at top level

Total memory size is 128 Kbytes

With the following information given:

Any kind of help would be awesome

NE-F15 a 16-l compuiar wlth load/ore architacture. Daign and tast thls archltaciure using Varlos NEW-F15 has a regstsr -bit FLAC reglster, and stxtssn Instruclons. Ths reglstsr Els compeisss sixteen 16-bit register; Ragister $0 is hardwired to 0x0000. Register $15 serves as Return Address registar for the CALL instruction. The FLAC register contains three bits Zero Z. Overflow M, and Sign NEW -F15s nstrucions can be catsgortzad tnto sour major claae: Arlthmstte, Memory, Load Immediata and Control Eight arthmetic and logical nstrucicns belong to this catsgory. Thay are ADD, PADDSB, SUB, NAND, XOR, SLL, SRL, SRA. Ths ADD, PADDSB, SUB, NAND, and XOR, Instructlors have a thras-address format. Tha asembly lavsl ayntax for thea inatructons is Opcode rd, U The two operands are: (%) and (A) and the destination is register rd. The ADD, PADDSB, and SUB instrucetons respacvely add, parallal add split bys, and subtraca tha two oparands -in wo s-complemard represantaion and sae tharaul in rgsar rd. The ADD and SUB instructions will use saturatine arithmetic. Meanng a result exceeds the most posllve number (215-1) then tha resul i saturatsd to 215-1) Lkelse k tka result were tc underlow the mo ragatre numbr (-2 15 than the result would be saturatsd to-2 15. The PADDSB nstrucion performs two byis-wse addiicns n parallal to ralizs sui-uerd paralelism Spacltcally tka hichar byba and tha lower bs w be traiad as two ssparate numbars stored ln a aing* word as a bys racto. han PADDSB s parformsd, ths two numbars will be addad ssparatsiy. To b* more gpeciei, let the contents in andare where ar b,c,d,f,&, and h e (Q1). Then after execution of PADDSB, the content of ed.will be rspacttvaly ahould ba saturatsdsaparaisly, maaning a rasul: axds the moat posive number (27-1) than th. razult is saturabed to(27-1), ard tf tha r«sult ware to underlo tha mo negatrs number (27) then the reault would be saturatad to -2A7 Ths NAND, and XOR Instructicns respectvely perrm bwtse NAND, and blewiss XOR, operatlors on the two oparands and save tha r«sult in regsrrd. The SLL, SRL, SRA, and nstrucions ha the following asambiy l«vel syntax.

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