In this problem, we explore cache mapping and cache replacement policies when me

Question

In this problem, we explore cache mapping and cache replacement policies when memory references are cyclic or periodic. Such reference streams are common in accesses to instructions (loops) or in strided accesses to data.

First-level instruction caches are often direct-mapped, not only because direct-mapped caches are faster on a hit, but also because they are better at handling loops than setassociative caches.

Assume a cache with four lines (0, 1, 2, and 3) and a cyclic (periodic) block reference string with block addresses (0,1,2,3,4,5)10. This notation means that the reference string has a periodic pattern of accesses to block addresses 0, 1, 2, 3, 4, and 5 repeated ten times. We classify misses into cold, capacity, and conflict misses. Capacity misses are counted in a fully associative (FA) cache with LRU replacement policy. In all cases the caches are empty at the beginning of the string.

(a)  Count the total number of misses in the following caches: direct-mapped, FA with LRU replacement, FA with FIFO replacement, FA with LIFO (last in first out) replacement, and a two-way set-associative cache with LRU in each set.

(b)  Based on your results in (a), what is the number of cold, capacity, and conflict misses for each cache?

Explanation / Answer

-> Number of Misses
Direct Mapping -> 60 (every time we need to remove address from the cache) since we have every addrees mapped to a perticular memory.

suppose address is 5, then we have 5%4 = 1 memory for this address.

-> FIFO
60 as again we again have to remove each address for accessing the new one.

-> LRU
60 because we are refering page in a sequence.

-> LIFO
4*10 = 40 + 2 = 42 as everytime onle 2,3,4 and 5 are a miss and for the very first time 0 and 1 are also a miss.

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