The table below lists a sequence of loads and stores in the LSQ, when their one/
ID: 3762966 • Letter: T
Question
The table below lists a sequence of loads and stores in the LSQ, when their one/two input operands are made available, and their computed effective addresses. Estimate when the address calculation happens for each ld/st and when each ld/st accesses the data memory. Assume that the processor does no memory dependence prediction to speculatively issue loads.
LD/ST
Address Reg.[1]
Store Reg[2]
Effective Address
LD
2
-
abcd
ST
7
10
abde
LD
5
-
abde
LD
3
-
abcd
ST
3
4
abde
LD
1
-
abde
LD
4
-
abcd
[1] The register for the address calculation is made available
[2] The register that must be stored into memory is made available
LD/ST
Address Reg.[1]
Store Reg[2]
Effective Address
LD
2
-
abcd
ST
7
10
abde
LD
5
-
abde
LD
3
-
abcd
ST
3
4
abde
LD
1
-
abde
LD
4
-
abcd
Explanation / Answer
Answer:
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he purpose is to design a computer that maximizes performance while keeping power consumption in check, costs low relative to the amount of expected performance, and is also very reliable. For this, many aspects are to be considered which includes Instruction Set Design, Functional Organization, Logic Design, and Implementation. The implementation involves Integrated Circuit Design, Packaging, Power, and Cooling. Optimization of the design requires familiarity with Compilers, Operating Systems to Logic Design and Packaging.
Instruction set architecture:
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n instruction set architecture (ISA) is the interface between the computer's software and hardware and also can be viewed as the programmer's view of the machine. Computers do not understand high level languages which have few, if any, language elements that translate directly into a machine's native opcodes. A processor only understands instructions encoded in some numerical fashion, usually as binary numbers. Software tools, such as compilers, translate high level languages, such as C, into instructions.
Besides instructions, the ISA defines items in the computer that are available to a program—e.g. data types, registers, addressing modes, and memory. Instructions locate operands with Register indexes (or names) and memory addressing modes.
The ISA of a computer is usually described in a small book or pamphlet, which describes how the instructions are encoded. Also, it may define short (vaguely) mnenonic names for the instructions. The names can be recognized by a software development tool called an assembler. An assembler is a computer program that translates a human-readable form of the ISA into a computer-readable form. Disassemblers are also widely available, usually in debuggers, software programs to isolate and correct malfunctions in binary computer programs.
ISAs vary in quality and completeness. A good ISA compromises between programmer convenience (more operations can be better), cost of the computer to interpret the instructions (cheaper is better), speed of the computer (faster is better), and size of the code (smaller is better). For example, a single-instruction ISA is possible, inexpensive, and fast, (e.g., subtract and jump if zero. It was actually used in the SSEM), but it was not convenient or helpful to make programs small. Memory organization defines how instructions interact with the memory, and also how different parts of memory interact with each other.
During design emulation software can run programs written in a proposed instruction set. Modern emulators running tests may measure time, energy consumption, and compiled code size to determine if a particular instruction set architecture is meeting its goals.
Implementation:
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Once an instruction set and micro-architecture are described, a practical machine must be designed. This design process is called the implementation. Implementation is usually not considered architectural definition, but rather hardware design engineering. Implementation can be further broken down into several (not fully distinct) steps:
For CPUs, the entire implementation process is often called CPU design.
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