Even if multiple interrupt requests are pending, only one request will be handle

Question

Even if multiple interrupt requests are pending, only one request will be handled for
each entry into ILOC in code showed below. True or false? Explain.

Interrupt handler
ILOC: Subtract SP, SP, #12 Save registers.
Store LINK_reg, 8(SP)
Store R2, 4(SP)
Store R3, (SP)
MoveControl R2, IPENDING Check contents of IPENDING.
And R3, R2, #4 Check if display raised the request.
Branch_if_[R3]0 TESTKBD If not, check if keyboard.
Call DISR Call the display ISR.
TESTKBD: And R3, R2, #2 Check if keyboard raised the request.
Branch_if_[R3]0 NEXT If not, then check next device.
Call KISR Call the keyboard ISR.
NEXT: Check for other interrupts.
Load R3, (SP) Restore registers.
Load R2, 4(SP)
Load LINK_reg, 8(SP)
Add SP, SP, #12
Return-from-interrupt
Main program
START: Set up parameters for ISRs.
Move R2, #2 Enable interrupts in
StoreByte R2, KBD_CONT the keyboard interface.
Move R2, #4 Enable interrupts in
StoreByte R2, DISP_CONT the display interface.
MoveControl R2, IENABLE
Or R2, R2, #6 Enable interrupts in
MoveControl IENABLE, R2 the processor control register.
MoveControl R2, PS
Or R2, R2, #1
MoveControl PS, R2 Set interrupt-enable bit in PS.
next instruction
Keyboard interrupt-service routine
KISR:
...
Return
Display interrupt-service routine
DISR:
...
Return

Explanation / Answer

Even if multiple interrupt requests are pending, only one request will be handled for
each entry into ILOC in code showed below. True

The program must initilize any variable needed by the interrupt service routine,such as memory buffer pointers.then it interrupt in both interface.It enable interrupt in the processor control register IENABLE.Finally the processor is enable to respond to interrupts in general by setting to 1 the IE bit in the processor status register ,PS.The processor will automatically save the content of the Program Counter (PC) and the load the address ILOC into PC.

These are all steps handle these code of program

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