The timing diagram shown on a RISC processor where the I and E stages can be exe

Question

The timing diagram shown on a RISC processor where the I and E stages can be executed

The timing diagram shown below is for the execution of 5 instructions on a RISC processor where the I and E stages can be executed simultaneously, but the system bus configuration requires stage D to be executed by itself. If a dual-port RAM removes the restriction that stage D executes by itself, what would be the resulting saving in the number of cycles for these instructions? Draw the revised timing diagram. Be sure to consider all pipeline hazards and assume that instructions cannot be reordered. Also, assume that LOAD operations are slow to the point that the next instruction after a LOAD cannot use the loaded valued, but any later instruction can use the value. LOAD A leftarrow M I E D ADD C leftarrow A+5 I E LOAD B leftarrow M I E D COMPARE B leftarrow C I E BRANCH EQ X I E NOOP I E STORE M leftarrow C I E D

Explanation / Answer

Normally RISC processor reduced instruction set computer in this instructions are all arithamatic instuction are sumitansely loa and as well process so that in this programme add insruction and compare instruction are simultaneously excuted

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