An inverted page table can be used to further optimize space and time. How many

Question

An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss?

The following table shows the contents of a 4-entry TLB.

a.   Under what scenarios would entry 2’s valid bit be set to zero?

What happens when an instruction writes to VA page 30? When would a software managed TLB be faster than a hardware managed TLB?

What happens when an instruction writes to VA page 200?

Explanation / Answer

3 or fewer PTEs will be required to store the page table as there are only 3 valid entty-ids.

Again it will be 3 or fewer to server a TLB miss as it is a 4 entry TLB

a)

Any address will be fine for the hit as long as the number of hits are correct for the scneario. It should be 3 in this case.

b)

It will be a TLB miss.

It will evict one block and in some case hardware TLB will be faster when the prediction is correct in the TLB and when there is a TLB hit

c)

It will not be allowed and an exception will be raised as there is only read only protection for the following tlb. If we try to write then there will be a exception.

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