Based on the information regarding the traffic light in the first picture, devel

Question

Based on the information regarding the traffic light in the first picture, develop the verilog code pertaining to the specific states of the light signals.

You want to build a system in Verilog (there is a start template that is called light module below) that controls four stop lights that only have red and green: IAS CIB sB There are 4sensors labelled sA, sB, sC, and sD, and these sensors will have a value of1 when there is a car and 0 when there is no car. Also, there are 4 corresponding lights labelled IA, IB, IC, and ID, respectively. These lights are 2 bit signals that when an input of "00" is sent and the stoplight will go Green and the cars will go through the traffic light and an input of "01" is a Red and the cars will not go through (note that IA controls cars going East and IC controls cars going West- independently). Finally, the systenm also has a reset (normal operation mode is 1) and a clock that has a clock rate of 60Hz Normal - Sequence: Build the light so that when there are no cars one traffic light will be green and the other three will be red and each direction will get the green in a clockwise direction (IAIDICIB>IA...) changing every X seconds where X is the number of letters in your name ("Peter Jamieson" 13 seconds). This sequence will be broken if a car arrives on a sensor. Assume cars arrive at the traffic light no less than 120 seconds apart from each other. When a car arrives at a sensor, turn the respective light green in X/2 (rounded down) seconds and keep it on for X seconds. If the respective light is already on then make it stays green for X more seconds. Once this is done start go back to the Normal-Sequence. Finally you must build a counting module as started below that will interact with your design.

Explanation / Answer

type verilog code on verilog editor and run observe the output on any simulator

module car(clk, rst, sa,sb,sc,sd,ia,ib,ic,id);
input clk , rst
input sa,sb,sc,sd;
output[1:0] ia,ib,ic,id;
reg [1:0]ia,ib,ic,id;
always @(posedge clk);
if clk='1' and rst ='1'
ia<=null;
ib<=null;
ic<=null;
id<=null;
elsif clk='1' and rst='0' and sa='1';
ia<='1';
elsif clk='1' and rst='0' and sb='1';
ib<='1';
elsif clk='1' and rst='0' and sc='1';
ic<='1';
elsif clk='1' and rst='0' and sd='1';
id<='1';
else
(ia='0',ib='0',ic='0',id='0');
endmodule

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