Which CPU has more complicated control unit RISC or CISC?.... b) Which CPU can u

Question

Which CPU has more complicated control unit RISC or CISC?.... b) Which CPU can use faster clock signal, RISC or CISC?.... a) What type of a CPU is MIPS?.... b) Is CPU with two pipelines superscalar?.... a) What does ILP stand for?.... b) Can pipelined ILP designed CPU execute instructions of two program threads at the same time?.... a) What generation of a programming language is RTL? (Circle) a.1) -1GL a.2) 0GL a.3) 1GL a.4) 3GL Write one RTL instruction of your choice:.... and explain what does it do?.... a) What does HBA stand for?.... b) What software is necessary to convert HBA into a set of software functions callable by the OS kernel's I/O management module?.... a) What does RISC stand for?.... b) What does CISC stand for?.... a) Is VMMU a paging AU?.... b) Can VMMU generate an interrupt? a) Is cache memory a memory or a device?.... b) Does L2 cache keep instruction and data separated?.... a) How many limes is typical DRAM memory faster than the typical hard disk device?.... b) Can CPU read or write data into the DRAM based systems memory during the memory refresh operation?.... a) What does DRAM controller do during the refresh operation?.... b) Does every pipeline in a superscalar CPU have an ALU?

Explanation / Answer

1.a)CISC

b)CISC

2.A)RISC

B)TRUE

3.A)Instruction-level parallelism (ILP)

B)YES

4.A)3GL

B)

RTL describes the hardware you want by implying logic. defining flip-flops, latches and how data is transfered between them. This is synthesizable, synthesis may alter/optimize the logic used but not behavior. Switching muxes for gates etc some times inverting signals to better optimize the design.

Verilog RTL implying a flip-flop:

5.A)host bus adapter (HBA)

B)HBAs are integral parts of a SAN environment. "Typically, the HBA will be recognized by the SAN management software

6.A)RISC (reduced instruction set computer)

b)complex instruction set computer (CISC)

7.A)

8a)memory device

b)not separated

9.A)I'm surprised: Figure 3 in the middle of this article, The Pathologies of Big Data, says that memory is only about 6 times faster when you're doing sequential access (350 Mvalues/sec for memory compared with 58 Mvalues/sec for disk); but it's about 100,000 times faster when you're doing random access

b)While a refresh cycle is occurring the memory is not available for normal read and write operations

10.a)his refresh activity is done by a DRAM controller that rewrites all of the memory cells.

b)yes

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