Consider the usage of critical word first and early restart on L2 cache misses.

Question

Consider the usage of critical word first and early restart on L2 cache misses. Assume a 1 MB L2 cache with 64 byte blocks and a refill path that is 16 bytes wide. Assume that the L2 can be written with 16 bytes every 4 processor cycles, the time to receive the first 16 byte block from the memory controller is 120 cycles, each additional 16 byte block from the memory requires 16 cycles, and data can be bypassed directly into the read port of the L2 cache. Ignore any cycles to transfer the miss request to the L2 cache and the requested data to the L1 cache.
a. How many cycles would it take to service an L2 caches miss with and without this technique (critical word first and early restart)?
b. Do you think critical word first and early restart would be more important for L1 caches or L2 caches, and what factors would contribute to their relative importance?

Explanation / Answer

a) without critical word first and early restart:

wait for the entire 64 byte(block of size L2) to be transferred to the L2

number of 16 bytes chunks=64/16=4

time(in cycles) =cycles for first chunk+ cycles for remaining three chunks

it requires 120 cycles for the first 16 bytes and 16 cycles for the next 3 cycles each

number of cycles=(1*120)+(16*3)=168

with critical word first and early restart:

wait for only first 16 byte to be trabsferred to the L2

time(in cycles)=time to transfer 16 bytes

number of cycles=(1*120)=120

b. critical word first and early restart techniques have an impact when the block sizes are large. Since these techniques aim to reduce the miss time, their impact will depend on the number of misses happening in L1 or L2. L2 caches always have larger block sizes and work at a better rate than L1. This implies that the techniques of critical word first and early restart can show some impact on the performance of L2 caches.

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