A CPU is designed to execute one instruction in the following 5 stages: (1) fetc

Question

A CPU is designed to execute one instruction in the following 5 stages: (1) fetch the next instruction from memory and save it in Instruction Register (IR); (2) modify Program Counter (PC) to point to the next instruction; (3) Decode the instruction in IR; (4) Fetch operands; (5) ALU performs the calculation. Assuming each stage needs 2ns to complete its job, How long does it take for this computer to complete one instruction execution? What's the MIPS this computer can achieve with this pipeline (parallelism) design.

Explanation / Answer

a) To complete one instruction execution ,we know that

instruction cycle = fetch cycle + exceute cycle

Fetch cycle takes more number of machine cycle when compair to Execute cycle,for example if we have 7 machine cycle in that 4 machine cycle will be alloted to fetch operation and the remainng 3 for execute cycle

Therefore the

instruction cycle = 2ns + 2ns

=4ns

b) when the above tast is in in process to execute the instruction the next instruction will be in the pipeline , hence this kind of processing is know as parallelism

for example:

consider an ASM language of 8085 processor , the machine instruction are

LDA 8500H

MOV B,A

LDA 8501H

ADD B

STA 9500H

HLT

In the above code first it loads the given instruction LDA 8500H ,whose machine code or opcode is 3ah into the instruction register and then it decode it and plcae the data into register A

Now the next instruction is MOV B,A which will move the content of register A into register B

Later it then loads the given instruction LDA 8501H ,whose machine code or opcode is 3ah into the instruction register and then it decode it and plcae the data into register A

Now the ALU will perform the addition of both, the content of register A and register B with an instruction ADD B and then finally the result is stored into the memory location of 9500H

Hence this kind of achieving the instruction one after the other and placing the next upcoming instruction into a pipe is know as pipilining and processing the task is called parallelism

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