Assume the individual stages of the datapath have the following latencies: IF: 3

ID: 3770532 • Letter: A

Question

Assume the individual stages of the datapath have the following latencies:

IF: 350 ps

ID: 450 ps

EX: 150 ps

MEM: 300 ps

WB: 200 ps

Assume the instructions executed by the processor are broken down as follows:

ALU: 45%

Beq: 20%

LW: 20%

SW: 15%

What is the clock cycle time in a pipelined and non-pipelined processor?

Pipelinied: 150ps, Non-pipelined: 150ps

Pipelinied: 450ps, Non-pipelined: 1450ps

Pipelinied: 150ps, Non-pipelined: 1250ps

Pipelinied: 300ps, Non-pipelined: 300ps

Pipelinied: 150ps, Non-pipelined: 150ps

Pipelinied: 450ps, Non-pipelined: 1450ps

Pipelinied: 150ps, Non-pipelined: 1250ps

Pipelinied: 300ps, Non-pipelined: 300ps

Answer is option (b)

Explantion:

Pipelined Processor-

- Pipelining is the process used for reducing cycle time.

- In pipelined processor the cycle time is the time taken for the longest individual stage of the data path and the register delay.

So the Cycle time in pipelined processor is :

CT = ID + Register Delay

CT =450ps + 0ps (Since there is no register delay)

CT = 450ps

Non-Pipelined Processor-

- As there is no pipeling the cycle time allows the instruction to go through all the five stages in one cycle

CT= IF+ID+EX+MEM+WB

CT = 350ps+450ps+150ps+300ps+200ps

CT= 1450ps

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.