1. For the following instructions, what is the minimum stall cycles that are nee

Question

1. For the following instructions, what is the minimum stall cycles that are needed after the beq instruction?

Beq r5,r4,label

Add r10,r10,r14

a. 0

b. 1

c. 3

d. 2

2. Suppose that in 100 memory references there are 4 times misses in the first level cache and 2 misses in the second level cache. What are the various miss rates?

a. L1 cache miss rate = 4% and L2 miss rate = 2%

b. L1 cache miss rate = 4% and L2 miss rate = 60%

c. L1 cache miss rate = 4% and L2 miss rate = 50%

d. L1 cache miss rate = 0.4% and L2 miss rate = 60%

Explanation / Answer

a)

The minimum stall cycles would obviously be 0 in case the branch is not taken. The processor won't jump to the branch location and therefore add will be as the next instruction in the pipeline. It will be processed. So minimum stall cycle will be zero.

b)

There are 100 operations in total. Now L1 has 4 misses so miss rate = 4/100 * 100 = 4%

Now all the misses from l1 will go to L2 cache. Now in l2 cache 2 misses are there.

so miss rate = 2/4 * 100 = 50%

so L1 miss rate = 4% l2 miss rate = 50%

correct option is C.

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