Assume a base CPI of 1.2 without branching. Assume 15% of instructions are condi

Question

Assume a base CPI of 1.2 without branching. Assume 15% of instructions are conditional branches and 5% are unconditional branches. 60% of conditional branches are taken. With no prediction, the branching penalty is 8 cycles for a conditional branch taken and 6 cycles for an unconditional branch taken. The branch prediction is 80% accurate, and 90% of all branch targets are in the branch target buffer. If the branch target is known and the branch is correctly predicted, there is no branching penalty. If the branch is correctly predicted, but the branch target is not known, the penalty is 6 cycles. Mis-predictions result in an 8 cycle penalty. What is the speed up gained by adding the branch prediction?

Explanation / Answer

Base CPI =1.2

CPI latency = 0.15 *0.6*1.2=0.108

Consider the datapath for the load instruction since, it requires all the functional blocks in the data path.

The cost is always the total cost of all components (not just those on the critical path, so the original processor has a cost of I-Mem, Regs, Control, ALU, D-Mem, 2 Add units and 3 Mux units.

The total cost of load instruction without improvement is

                                      = 1000 + 200 + 500 + 100 +2000 + 2 × 30 + 3 × 10

                                    = 3890.

Cost with improvement for critical path ((I-Mem, Larger Regs, Control, ALU, D-Mem, 2 Faster Add units and 3 Mux unit) is

                                      =1000 + (200 +200) + 500 + 100 + 2000 + (2 *30) + (3 * 10)

                                      = 4090

Relative cost = 4090/3890

                      = 1.05

Cost/performance ratio = relative cost/speed up

                                      = 1.05/0.97

                                      = 1.08

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