1. Address Translation (20 points) Below, you are provided with a snapshot of a
ID: 3776613 • Letter: 1
Question
1. Address Translation (20 points) Below, you are provided with a snapshot of a 4 entry, fully associative TLB (translation lookaside buffer) and a page table. If needed, you may assume that the value of the page table register is 0 VALUE PARAMETER Page 4 associativity fully associative Replacement policy LRU-the entry that has not been used for the longest time will be evicted if a new entry is to be added Initial TLB State TLB INTERPRETATION COLUMN VALUE MEANING Entry is not valid (TLB miss) Entry is valid (TLB hitl o Data has not been modified DIRTY 1 Data has been modified 1 Most recently used 4 least recently used TLB TABLE VALID DIRTY TAG PHyssiCAL PAGER 1 0 2 0101 0111 1 3 1100 1011 1 0 1 0001 2001Explanation / Answer
The page table for a process/program can be huge – and the entire page table will almost certainly not be cacheable. - As a page table reference is required for every address translation, if every instruction and every data reference required a main memory lookup, performance would quickly and significantly degrade. - The TLB is a fast cache for part of the page table – and if (a) the TLB contains 64-128 entries and (b) each page has 214 – 216 addressable entries, the seemingly small TLB can provide wide coverage For the next question, refer to the snapshot of TLB and page table state shown below. Initial TLB State: (Note that 1 = “Most Recently Used and 4 = “Least Recently Used”) Valid LRU Tag Physical Page # 1 3 1111 0001 1 4 0011 0010 1 2 1000 1000 1 1 0100 1010 Initial Page Table State: Valid Physical Page # 0000 0 0011 0001 1 1001 0010 1 0000 0011 1 0010 0100 1 1010 0101 0 0100 0110 1 1011 0111 0 0101 1000 1 1000 1001 1 0110 1010 1 1111 1011 1 1101 1100 1 0111 1101 0 1110 1110 1 1100 1111 1 0001 Also: 1. Pages are 4 KB 2. There is a 4-entry, fully-associative TLB 3. The TLB uses a true, least-recently-used replacement policy.
Our VPN is 16 bits long – so each page table will have 216 entries - There are also 16 bits left over for offset - Thus, each physical frame number is 30 – 16 = 14 bits - Each page table entry will hold the above 14 bit PFN + 1 valid bit + 1 dirty bit o Thus, each page table entry is 2 bytes. - There are 216, 2-byte entries per process o Thus, each page table requires 217 bytes – or ~128 Kbytes - Because each process has its own page table, a total of 218 bytes – or ~256 Kbytes are needed.
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