In this module, each group will submit their proposed processor architecture. In
ID: 3777817 • Letter: I
Question
In this module, each group will submit their proposed processor architecture. In addition, each group member must also include a page that describes each member’s role, their involvement in the group project activity and a brief description of your group meeting. In your proposed architecture, specify the following: Determine the memory structure used in your computer architecture. You may choose to have a unified memory for both data and instructions or you may prefer a separate memory for each. Determine the size of your proposed memory. . Determine what instructions can access the memory and how. In the previous milestone, you determined all the instructions that can be handled in the proposed computer architecture. In this milestone, determine what instructions can access the memory and how. Determine the cache levels. You may choose to have one or more cache levels. In each cache level, you have to determine if this level is a unified or a separate cache for both data and instructions. In addition, you have to select the cache size for each level. Determine how cache works. Determine how to locate a block in the cache, and how to choose a block to be replaced from the cache
Explanation / Answer
The memory structure to be used will involve will be system global area which has both data and information together .The data is processed within the same memory and we will have processed data within the same area.The size will be 2gb(gigabytes) which is normal for the laptop users.The instructions that access memory are fetch instructions.These instructions are processed and decoded and the output is send to information.
There are 3 cache levels.The first one is the Level 1 Cache(2KB - 64KB) - It includes the various Instructions which are first searched in this cache.This cache very small in comparison to others, thus making it faster than the rest.On the other hand we have Level 2 Cache(256KB - 512KB) - In this cache,if the instructions are not present in the L1 cache then it looks in the L2 cache, which is a slightly larger pool of cache, thus accompanied by some latency.The final cache is the level 3 cache (1MB -8MB) -In this cache, with each cache miss, it proceeds to the next level cache.This is a very unique cache as it is the largest among the all the cache, even though it is slower, its still faster than the RAM.
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