I have a problem with Makefiles, i understand the point behind them but they are

Question

I have a problem with Makefiles, i understand the point behind them but they are very hard to understand -

the programming in itself is not difficut, but making them work in Linux through makefiles is extremely difficult

Can somebody please explain this to me? and please input the changes!

Thankyou very much in advance

SOURCES=main.cpp part1.cpp part2.cpp
OBJECTS=$(SOURCES :.cpp=.o)
DEPS=$(SOURCES :.cpp=.d)
EXE=prog
CXXFLAGS=-I.

# Making for host
# > make ARCH=host
ifeq (${ARCH},host)
CXX=g++
BUILD_DIR=build/host
endif

# Making for target
# > make ARCH=target
ifeq (${ARCH},target)
CXX=arm -devkit -g++
BUILD_DIR=build/target
endif

$(EXE): $(DEPS) $(OBJECTS) # << Check the $(DEPS) new dependency
$(CXX) $(CXXFLAGS) -o $@ $(OBJECTS)

# Rule that describes how a .d (dependency) file is created from a .cpp file
# Similar to the assigment that you just completed %.cpp -> %.o
${BUILD_DIR }/%.d: %.cpp
$(CXX) -MT${BUILD_DIR }/$(@:.d=.o) -MM $(CXXFLAGS) $^ > $@

ifneq ($(MAKECMDGOALS),clean)
-include $(DEPS)
endif

SOURCES=main.cpp part1.cpp part2.cpp
OBJECTS=$(SOURCES :.cpp=.o)
DEPS=$(SOURCES :.cpp=.d)
EXE=prog
CXXFLAGS=-I.

# Making for host
# > make ARCH=host
ifeq (${ARCH},host)
CXX=g++
BUILD_DIR=build/host
endif

# Making for target
# > make ARCH=target
ifeq (${ARCH},target)
CXX=arm -devkit -g++
BUILD_DIR=build/target
endif

$(EXE): $(DEPS) $(OBJECTS) # << Check the $(DEPS) new dependency
$(CXX) $(CXXFLAGS) -o $@ $(OBJECTS)

# Rule that describes how a .d (dependency) file is created from a .cpp file
# Similar to the assigment that you just completed %.cpp -> %.o
${BUILD_DIR }/%.d: %.cpp
$(CXX) -MT${BUILD_DIR }/$(@:.d=.o) -MM $(CXXFLAGS) $^ > $@

ifneq ($(MAKECMDGOALS),clean)
-include $(DEPS)
endif

Listing 3.1: Handling cross compiling properly 1 SOURCES main Cpp parti Cpp part2. cpp OBJECTS (SOURCES o) Cpp 3 DEPS-$ (SOURCES Cpp d) 4 EXE prog 5 CXXFLAGS -I 7 Making for host 8 make ARCH-host 9 ifeq ($1 ARCH host) 10 11 BUILD DIR-build /host 12 endif 13 14 Making for target 15 make ARCH target 16 ifeq ($1 ARCH) target) 17 CXX arm-devkit-g 18 BUILD DIR-build target 19 endif 20 21 22 (EXE) $(DEPS) COBJECTS) Check the (DEPS) new dependency 23 (CXX) $(CXXFLAGS) o $0 (OBJECTS) 24 25 Rule that describes how a d (dependency) file is created from a cpp file just completed 2. opp 26 Similar to the assigment that you 27 BUILD DIR d: Cpp 28 (CXX) MT BUILD DIR (0: d- o) MM (CXXFLAGS) 29 30 ifneq (MAK ECMDGOALS clean) 31 include $(DEPS) 32 endif IIST OF THINGS TO CHANGE Things to alter: Objects placement nou As it is now, w here are the objects placed? Why is this bad? Objects placement after change Where are they to be placed now? Explain how this is achieved Program file Is the current placement the correct one Hardly; what to do and where to place it Hints: Checkout the make command $(addprefix). Ensuring that the dependency files are generated in the correct spot has already been fixed. Furthermore what should the target be??? Suggestion Place all generated object files in build/target or build/host (this is what has already begun in the above makefile listing) respectively. Place the executable in bin/target or bin/host respectively.

Explanation / Answer

Makefiles are a simple way to organize code compilation.

gcc -o (filename) -I

(The -I. is included so that gcc will look in the current directory for your file)

This code will compile the files

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