Your task is to compare the memory efficiency of four different styles of instru

Question

Your task is to compare the memory efficiency of four different styles of instruction set architectures. The architecture styles are

Accumulator—All operations occur between a single register and a memory location.

Memory-memory—All instruction addresses reference only memory locations.

Stack—All operations occur on top of the stack. Push and pop are the only instructions that access memory; all others remove their operands from the stack and replace them with the result. The implementation uses a hardwired stack for only the top two stack entries, which keeps the processor circuit very small and low cost. Additional stack positions are kept in memory locations, and accesses to these stack positions require memory references.

Load-store—All operations occur in registers, and register-to-register instructions have three register names per instruction.

To measure memory efficiency, make the following assumptions about all four instruction sets:

All instructions are an integral number of bytes in length.

The opcode is always one byte (8 bits).

Memory accesses use direct, or absolute, addressing.

The variables A, B, C, and D are initially in memory.

Invent your own assembly language mnemonics (examples in lecture note provides a useful sample to generalize), and for each architecture write the best equivalent assembly language code for this high-level language code sequence:

A=B-C;

B=A-C;

D=A+B;

b) Label each instance in your assembly codes for part (a) where a value is loaded from memory after having been loaded once. Also label each instance in your code where the result of one instruction is passed to another instruction as an operand, and further classify these events as involving storage within the processor or storage in memory.

c) Assume that the given code sequence is from a small, embedded computer application, such as a microwave oven controller, that uses a 16-bit memory address and data operands. If a load-store architecture is used, assume it has 16 general-purpose registers. For each architecture answer the following questions: How many instruction bytes are fetched? How many bytes of data are transferred from/to memory? Which architecture is most efficient as measured by total memory traffic (code + data)?

Explanation / Answer

Accumulator Instructions The assignment would be translated into the following instructions in an accumulator instruction set: load AddressB # Acc = Memory[AddresB] or Acc = B add AddressC # Acc = B + Memory[AddresC] or Acc = B + C store AddressA # Memory[AddresA] = Acc or A = B + C All variables in a program are allocated to memory in accumulator machines, instead of normally to registers as we saw for MIPS. One way to think about this is that variables are always spilled to memory in this style of machine. As you may imagine, it takes many more instructions to execute a program with a single-accumulator architecture. Memory-Memory Instructions The assignment would be translated into the following instructions in a memorymemory instruction set: add AddressA, AddressB, AddressC Stack Instructions The assignment would be translated into the following instructions in a stack instruction set:

push AddressC # Top = Top+4; Stack[Top] = Memory[AddressC]

push AddressB # Top = Top+4; Stack[Top] = Memory[AddressB]

add # Stack[Top-4] = Stack[Top] + Stack[Top-4]; # Top = Top-4

pop AddressA # Memory[AddressA] = Stack[Top]; Top = Top - 4

Load-Store Instructions The assignment would be translated into the following instructions in a load-store instruction set:

load r1 AddressB # r1 = Memory[AddressB] load r2

AddressC # r2 = Memory[AddressC]

add r3 r1 r2 # r3 = r1 + r2

store r3 AddressA # Memory[AddressA] = r3

For a given code sequence, we can calculate the instruction bytes fetched and the memory data bytes transferred using the following assumptions about all four instruction sets: • The opcode is always 1 byte • All memory addresses are 2 bytes • All data operands are 4 bytes • All instructions are an integral number of bytes in lengt

Code Size For example, a register load will require 4 instruction bytes (1 for the opcode, 1 for the register destination, and 2 for a memory address) to be fetched from memory along with 4 data bytes. A memory-memory add instruction will require 7 instruction bytes (1 for the opcode and 2 for each of 3 memory addresses) to be fetched from memory and will result in 12 data bytes being transferred (8 from memory to the processor and 4 from the processor back to memory). The following table displays a summary of this information for each of the architectural styles for the code

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