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First, write a Verilog code for a one-digit BCD adder Afterwards, write a Verilo

ID: 3792734 • Letter: F

Question

First, write a Verilog code for a one-digit BCD adder

Afterwards, write a Verilog code for the two-digit BCD adder by instantiating the one-

digit BCD adder module twice

Finally, simulate your two-digit BCD adder

I have the bcd code for one digit BCD but I'm having trouble with the top level.

module bcd1(cin, X, Y, S, cout);

   input cin;
   input [3:0] X,Y;
  
   output reg [3:0] S;
   output reg cout;
  
   reg [4:0] z;
  
   always @(X, Y , cin)
   begin
  
       z = X + Y + cin;
      
       if (z < 10)
      
           {cout, S} = z;
      
       else
      
           {cout, S} = z + 6;
   end
  
  
endmodule

For example, for 135 87 48: S2SIS0 A1A0 B1B0 0001 0011 0101 1000 0111 0100 1000 Al(4-bit) S204-bit) A004-bit) Two-digit S1(4-bit) BCD adder 104-bit S004-bit) B004-bit) B1 A1 B0 A0 ne-digit One-digit bcdadd. S2 S1 S0

Explanation / Answer

As per your question i am answering

BCD (Binary coded decimal) is a way of representing decimal digits in binary form.

In general we used 4 bits for representing 0 to 9.

Verilog code:-

module bcd_adder(a,b,carry_in,sum,carry);


  input [3:0] a,b;

  input carry_in;

output [3:0] sum;

output carry;

reg [4:0] sum_temp;

reg [3:0] sum;

reg carry;


//always block for doing the addition
always @(a,b,carry_in)

begin

sum_temp = a+b+carry_in; //add all the inputs

if(sum_temp > 9)

begin

sum_temp = sum_temp+6; //add 6, if result is more than 9.

carry = 1;

sum = sum_temp[3:0];   end

else   begin

carry = 0;

sum = sum_temp[3:0];

end

end

endmodule

Testbench for BCD adder:

module tb_bcdadder;

reg [3:0] a;

reg [3:0] b;

reg carry_in;

wire [3:0] sum;

wire carry;

bcd_adder uut ( .a(a),

.b(b),

.carry_in(carry_in),

.sum(sum),

.carry(carry)

);

initial begin

a = 0; b = 0; carry_in = 0;   #100;

a = 6; b = 9; carry_in = 0;   #100;

a = 3; b = 3; carry_in = 1;   #100;

a = 4; b = 5; carry_in = 0;   #100;

a = 8; b = 2; carry_in = 0;   #100;

a = 9; b = 9; carry_in = 1;   #100

end

endmodule