Given this processor hardware design and the control sequence below, describe in

Question

Given this processor hardware design and the control sequence below, describe in words (or C-like pseudo code) the function of the instruction xyzzy Srd. when op() op(l) Xyzzy Start: PCout, MARin, MEHread, Yin CONST(4), ALUadd, Zin, UNTILafc MDRout, IRin Zout, PCin, JUMPonop HALT/* Should end here on undecoded op */Xyzzy: SELrd, REGout, Yin SELrd, REGout, ALUadd, Zin Zout, ALUadd, Zin Zout, SELrd, RECin, JUMP(Start) Given the xyzzy Srt, Srs instruction as defined above, and assuming that a memory load request takes 4 clock cycles to complete (after MEMread has been issued), how many clock cycles would it take to execute each xyzzy instruction? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here: Given this processor hardware design, suppose that the following control state is the limiting factor in determining the maximum clock speed. Given that the propagation delay associated with zin is 1ns. MDRin is 2ns, REGout is 4ns. SELrs is 8ns. and ALUadd is 16ns. what is the period (in nanoseconds) of the fastest allowable clock? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here: MDRin, ALUadd, REGout, zin, SELrs Given this processor hardware design, add control states to the following to implement a convert-to-gray-code instruction (as decoded by the when below), such that gray srt, srs makes rt=rs (rs>>1);. Note that >> is a shift right logical operation.

Explanation / Answer

when op() op(1) Xyzzy

Start:
PCout, MARin, MEMread, Yin
CONST(4), ALUadd, Zin, UNTILmfc
MDRout, IRin
Zout, PCin, JUMPonop
HALT /* Should end here on undecoded op */

Xyzzy:
SELrd, REGout, Yin
CONST(-1), ALUxor, Zin
Zout, SELrd, REGin, JUMP(Start)

ANSWER :

rd=rd^-1; which is rd=(~rd); or rd=NOT(rd)

Related Questions

Navigate

• Browse (All)
• Browse G
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.