For this problem, assume that all branches are perfectly predicted (this elimina

Question

For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we change load/store instructions to use a register (without an offset) as the address, these instructions no longer need to use the ALU. As a result, MEM and EX stages can be overlapped and the pipeline has only 4 stages. Change this code to accommodate this changed ISA. Assuming this change does not affect clock cycle time, what speedup is achieved in this instruction sequence?

Explanation / Answer

Assume that $6 + 40 = $a, $2 + 50 = $b, $4 + 50 = $c,

Instruction sequence a

lw $1,$a – I1
beq $2,$0,Label ; Assume $2 == $0 – I2
sw $6,$b – I3
Label: add $2,$3,$4 – I4
sw $3,$c – I5

Instruction sequence b

lw $5,$d – I1
sw $4,$e – I2
lw $3,$f – I3
beq $2,$0,Label ; Assume $2 != $0 – I4

a : 5 stages -> 8 cycles

4 stages -> 7 cycles

Speedup = 8/7 = 1.14

b : 5 stages -> 9 cycles 4 stages -> 8 cycles Speedup = 9/8 = 1.13

t0 t1 t2 t3 t4 t5 t6 t7 IF 11 12 14 15 ID 11 12 14 15 EX 11 12 14 15 MEM 11 12 14 15 WB 11 12 14 15

Related Questions

Navigate

• Browse (All)
• Browse F
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.