Assume you have a 4 GHz CPU with a CPI of 1.0 (instructions on this CPU require

Question

Assume you have a 4 GHz CPU with a CPI of 1.0 (instructions on this CPU require 1.0 cycles per instruction on average) and a main memory access time of 100 ns. If the system misses 2.5% of the time, what’s the new effective CPI with one level of cache?

Use the equation Total CPI = Base CPI + Memory-stall cycles per instruction

Cock cycles are required for a main memory access 400. Add to the system in a second level of cache. Now a miss in L1 can be satisfied by a hit in L2 or by main memory. This L2 cache has an access time of 5 ns for either a hit or a miss, and is large enough to reduce the miss rate to main memory to 0.8%.   

Total CPI = _________________________________________ cycles per instruction

Explanation / Answer

4Ghz or 4*109 instructions per sec

therefore one instruction takes 0.25ns

therefore memory access creates a stall of 400 cycles (100/0.25)

therefore 97.5% takes 1 clock cycle
             2.5% takes 400 clock cycles

Therefore avg = (97.5*1 + 2.5*400) / 100 = 10.975
CPI = 10.975

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The CPU have 2.5% misses at level 1

out of 2.5% only 0.8% require memory access.

Now the new L2 cache needs 5ns or 20 clocks cycles

therefore new system needs:
   97.5% takes 1 clock cycle
   2.5% takes 20 clock cycles
     0.8% takes 400 clock cycles

Therefore avg = (97.5*1 + 2.5*20 + 0.8*400) / 100 = 4.675
CPI = 4.675

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