a. What is the total address space that can be covered by that mode? b. What wou

Question

a.    What is the total address space that can be covered by that mode?

b.   What would be the maximum size of an integer array, if the compiler would use this instruction?

2.   The classic IA32 (Intel Architecture, 32-bit) uses the following memory parameters.

o   The memory word is one byte.

o   The data bus is 128-bit wide.

o   The total address space is given by the 32-bit pointer size.

Assume that a desktop processor had 1 MByte of L2-cache, organized as directly memory mapped. Every cache line holds 16 bytes of data.

d.   What is the maximum memory size?

e.    How many memory blocks - defined by the size of a cache line - are there?

f.     Is the data bus width optimal? Explain.

g.   If all transfers go to cache, how many memory address lines do you really need?

h.   Assume that the given cache size does not include overhead (such as tags). How many lines can it hold?

i.     A full memory address is 32-bit wide (see above). For caching, it is split into the following parts. Indicate the width of each field (bits).

Tag

Cache Line #

Byte #

Tag

Cache Line #

Byte #

Explanation / Answer

1a.   This Instruction is in Indexed absolute addressing mode.
   Address space is the maximum amount of memory that a processor can address.
   In absolute address with index register operations, the contents of an index register are added to an absolute address to form an effective address in memory.
   The total address space would be two byte absolute addresses with contents of one of five index registers

1b.   As the instruction is indexed absolute addressing mode, using all the addressing components together allws efficient indexing of a two-dimensional array when the elements of the array are 2,4 or 8 bytes in size.

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