We have a 5-stage pipeline: • IF – instruction fetch • ID – instruction decode a

Question

We have a 5-stage pipeline:

• IF – instruction fetch

• ID – instruction decode and read registers

• EX – execute instruction or calculate address

• MEM – access memory

• WB – write results to registers

For each of the following blocks of code,

(i) determine if there are any pipeline hazards and, if so, what type is each (support this with a diagram showing the instructions moving through the pipeline). This will not be a structural hazard.

(ii) if there are pipeline hazards, for how many stages would the pipeline stall?

(iii) if there are pipeline hazards, reorder the code to avoid them without introducing new hazards while still accomplishing the same result.

(iv) note that there could be more than one hazard in a block of code; deal with all of them.

(a) ADD R1, R2, R3

ADD R4, R5, R6

STR R1, [R8]

STR R5, [R8, #4]

STR R6, [R8, #8]

(b) LDR R1, [R2]

ADD R2, R2, #4

LDR R3, [R2]

ADD R4, R1, R7

SUB R5, R6, R7

ORR R8, R6, R7

EOR R9, R6, R7

Explanation / Answer

(a)

MEM2

(i)Read after write data hazard occurs in STR R1,[R8]. There is only one hazard here.

(ii)for 1 stage , pipeline have to stall (if WRITE operation is performed in first cycle ) otherwise for 2 stages pipeline have to stall

(iii)Re-arranging the order

ADD R1, R2, R3

ADD R4, R5, R6

STR R5, [R8, #4]

STR R6, [R8, #8]

STR R1, [R8]

(b)

(i)

Data hazards : -

Structural hazards :-

(ii)

3 stages pipeline need to be stalled if write operation occurs in the first half of the cycle otherwise 4 stages

(iii)

1 2 3 4 5 6 7 8 9 ADD R1,R2,R3 IF ID EX MEM WB ADD R4,R5,R6 IF ID EX MEM WB STR R1,[R8] IF ID EX MEM1 MEM2 WB STR R5,[R8,#4] IF ID EX MEM1 MEM2 WB STR R6,[R8,#8] IF ID EX MEM1

MEM2

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