Given the following sequence of instructions in a pipelined MIPS processor: AND

Question

Given the following sequence of instructions in a pipelined MIPS processor:

AND $1,$1,$4

LW $4,40($1)

SUB $5,$3,$4

SW $2,20($1)

(a) For each instruction, identify if there is a data hazard. ecution and calculate the total number of cycles needed to complete executing the instructions. (c) If there is forwarding and hazard detection, complete the following table of cycles of the instruction sequence executin and calculate the total number of cycles needed to execute this instruction sequence. instruction sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AND $1,$1,$4 Lw $4,40(S1) SUB $5, $3,$4 SW $2,20($1) (d) For the first six cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in the table below Unit Signals 1 2 3 4 5 6 Hazard PCWrite Detection IF/Dwrite ID/EXZero Forwarding ForwardA Forward (e) If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes?

Explanation / Answer

(a)

AND $1,$1,$4 - No data hazard
LW $4,40($1) - data hazard
SUB $5,$3,$4 - data hazard
SW $2,20($1) - if WB occurs in firs half of cycle then there is no error,otherwise there is error

(b)

c)

It takes total 11 cycles

Instruction Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 15 AND $1,$1,$4 IF ID EX MEM WB LW $4,40($1) IF NOP NOP ID EX MEM1 MEM2 WB SUB $5,$3,$4 STALL STALL IF NOp NOP NOP ID EX MEM WB SW $2,20($1) IF ID EX MEM1 MEM2 WB

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