a. Write MIPs code to perform addition of two unsigned numbers in registers $t1

Question

a. Write MIPs code to perform addition of two unsigned numbers in registers $t1 and $t2 and then verify whether the result has overflowed the 32-bit long destination register $t3. Explain the overflow logic with comments to elaborate upon each line of MIPs code. b. Indicate with a diagram how the same logic can be implemented in hardware. c. Explain with a flow chart and architecture diagram hardware efficient division algorithm may be performed d. Explain why massively parallel implementation of the division algorithm not possible?

Explanation / Answer

Solution for PART D(as mentioned in the question):

In the case of the parallel implementation, the delay is reduced as there are independent branches for performing the task but the latency will increase dramatically as there will be only one division that will be performed by a single divider.

In this case the length of the parallel array increases four times in size each time the length of the word doubles and also the time taken for the execution also doubles. This exponential increase in the execution time can be handled using the concept of pipelining.

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