Using an FPGA programmed with Verilog design an instruction decoder. First decid

ID: 3816913 • Letter: U

Question

Using an FPGA programmed with Verilog design an instruction decoder. First decide what size instruction word you need based on the following attributes: 1. The instruction decoder must be able to control a 6-function ALU with a 4 times 4 bit register file (4 registers of 4 bits each) 2. The instruction decoder should allow "load immediate" and "add immediate" instructions 3. The instruction decoder should allow external memory read and write 4. The instruction decoder should allow "branch on zero" and "jump" instructions How many bits are needed? Staple your verilog code to this sheet and turn it in at the end of class

Explanation / Answer

32 bits are needed. As we need 4 registers of 4 bit each. That's makes a requirement of 16 bits memory. Addition of 16 bit to a 16 bit will need a memory of maximum 32 bits.

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Using an FPGA programmed with Verilog design an instruction decoder. First decid

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