Type 2b MEM data hazard: the conflict occurs between an instruction that is in t

Question

Type 2b MEM data hazard: the conflict occurs between an instruction that is in the MEM stage which has a value which will be written to a destination register when the instruction moves to the WB stage and the second source register of the instruction following the following instruction, i.e, the conflict is with register rd/rt of the first instruction and register rt of the third instruction. sub $t4, $t1, $t2 # $t4 is destination register ori $t7, $t7, 1 # For a MEM hazard, there must be an intervening instruction and $t3, $t0, $t4 $t4 is first source register

Explanation / Answer

IN the example above sub--and instructions which you have provided are in 2b type hazard.

MEM/WB.WriteReg = ID/EX.RegisterRt==> $t4

The sub --ori instruction is not a hazard as there is no dependency on $t7.

Related Questions

Navigate

• Browse (All)
• Browse T
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.